Designing Neuromorphic Hardware with Thermal Awareness Using Fractal-Based Interconnects

Abstract

Designing energy-efficient and thermally robust neuromorphic hardware is a growing challenge as computing systems scale to meet the demands of brain-inspired processing. Traditional von Neumann architectures face significant limitations due to the separation of memory and processing units, resulting in high latency and power dissipation. Neuromorphic systems, which mimic neural structures and dynamics, offer a promising alternative by enabling parallel and event-driven computation. However, the high density of synaptic interconnections in neuromorphic chips can lead to thermal hotspots, impairing performance, reliability, and longevity. This paper presents a novel approach to designing thermally-aware neuromorphic hardware by leveraging fractal-based interconnect topologies, specifically the Sierpinski carpet and Hilbert curve, to manage heat distribution while preserving connectivity and scalability. Fractal geometries, due to their inherent self-similarity and space-filling properties, enable efficient signal propagation and uniform thermal dispersion across the chip. We propose a design framework where neuron and synapse blocks are interconnected using fractal layouts that naturally facilitate heat spreading and minimize long interconnects. The architecture is evaluated through thermal simulations using finite element analysis (FEA) and compared against conventional mesh and tree interconnects. Results indicate up to 28% reduction in peak on-chip temperature and improved energy efficiency by 15%, without degrading computational accuracy or latency.